HALF ADDER - FULL ADDER - MUX
Truth Tables and Verilog Codes for one-bit Half Adder and Full Adder HALF ADDER By using half adder, you can design simple addition with the help of logic gates. Half Adder 0+0 = 0 0+1 = 1 1+0 = 1 1+1 = 10 These are the least possible single-bit combinations. But the result for 1+1 is 10, the sum result must be re-written as a 2-bit output. Thus, the equations can be written as 0+0 = 00 0+1 = 01 1+0 = 01 1+1 = 10 The output ‘1’of ‘10’ is carry-out. ‘SUM’ is the normal output and ‘CARRY’ is the carry-out. Half Adder Logic Circuit HALF ADDER TRUTH TABLE : S= A’B+AB’ C=AB If we want to write Verilog modules and testbench codes including every possible outcome, for Half Adder and Full Adder: HALF ADDER CODE: module halfandfull(A,B,C,S); input A,B; output C,S; assign C = A^B; assign S = A&B; endmodule HALF ADDER TEST BENCH CODE: module halffulltb; reg A;
